1. Technical Field
The present disclosure pertains to a circuit that includes a latch charge pump with equalization circuit and, more particularly to a charge pump having an equalization circuit to prevent malfunction during turning on and turning off of the charge pump.
2. Description of the Related Art
As is known, a charge pump is an electric circuit that performs the function of DC/DC converter and that avails itself of at least one capacitor, which is generally known as a “flying capacitor” and functions as an energy-storage element.
Operatively, the charge pump is such that, when it is supplied with a supply voltage Vdd, and it is connected to a load, it can supply to the load an output current IL and an output voltage Vout in which it is possible for the latter to be higher than the supply voltage Vdd.
Amongst charge pumps available on the market today, the so-called “latch charge pumps” are present.
In particular, patent application No. EP1881589, filed on Jul. 19, 2006, in the name of the present applicant, describes a latch charge pump, which is illustrated in FIG. 1, where it is designated as a whole by 1.
In greater detail, the latch charge pump 1, which in what follows is referred to briefly as “charge pump 1”, includes an input terminal IN, an output terminal OUT, a first enable terminal, and a second enable terminal, which are designated, respectively, by FX and FN, and at least two charge-pump stages. The charge-pump stages are connected in cascaded fashion between the input terminal IN and the output terminal OUT, and are connected, each, to the first enable terminal FX and to the second enable terminal FN. By way of example, shown in FIG. 1 are a first charge-pump stage and a second charge-pump stage, which are designated respectively by CBi-1 and CBi. More precisely, shown in FIG. 1 are, for simplicity of illustration, portions of the first charge-pump stage CBi-1 and of the second charge-pump stage CBi that are involved in operations of mutual charge sharing, these portions being described hereinafter.
In detail, the first charge-pump stage CBi-1 includes a first pump capacitor CUpi-1, connected between the first enable terminal FX and a first internal node Upi-1, and a second pump capacitor CDowni-1, connected between the second enable terminal FN and a second internal node Downi-1. In addition, the first charge-pump stage CBi-1 includes a first latch circuit Li-1, which is connected between the first internal node Upi-1 and the second internal node Downi-1, and is moreover connected to an intermediate node INT.
In turn, the first latch circuit Li-1 includes a first pump transistor MpU, which is connected between the intermediate node INT and the first internal node Upi-1, and has a first control terminal PgU. As illustrated by way of example in FIG. 1, the first pump transistor MpU can be a P-channel MOS transistor, the gate terminal of which corresponds to the aforementioned first control terminal PgU. As regards, instead, the drain and source terminals of the first pump transistor MpU, as likewise of all the transistors of a MOS type that will be mentioned and described hereinafter, they are generically referred to as “conduction terminals”, the distinction between drain terminal and source terminal being of no importance for the purposes of operation of the charge pump 1. In detail, one of the conduction terminals of the first pump transistor MpU is connected to the first internal node Upi-1, whilst the other is connected to the intermediate node INT.
The first latch circuit Li-1 further includes a second pump transistor MpD, which is of the same type as the first pump transistor MpU, connected between the intermediate node INT and the second internal node Downi-1, and which has a second control terminal PgD. The second pump transistor MpD is hence a P-channel MOS transistor, the gate terminal of which corresponds to the aforementioned second control terminal PgD. In addition, one of the conduction terminals of the second pump transistor MpD is connected to the second internal node Downi-1, whilst the other is connected to the intermediate node INT.
As regards the second charge-pump stage CBi, it includes a third pump capacitor CUpi, connected between the second enable terminal FN and a third internal node Upi, and a fourth pump capacitor CDowni, connected between the first enable terminal FX and a fourth internal node Downi. Furthermore, the second charge-pump stage CBi includes a second latch circuit Li, which is connected between the third internal node Upi and the fourth internal node Downi, and is moreover connected to the intermediate node INT.
In turn, the second latch circuit Li includes a third pump transistor MnU, which is connected between the intermediate node INT and the third internal node Upi, has a third control terminal NgU, and is of a type opposite to that of the first and second pump transistors MpU, MpD. The third transistor MnU is hence an N-channel MOS transistor, the gate terminal of which corresponds to the aforementioned third control terminal NgU. In addition, one of the conduction terminals of the third pump transistor MnU is connected to the third internal node Upi, whilst the other is connected to the intermediate node INT.
The second latch circuit Li further includes a fourth pump transistor MnD, which is of the same type as the third pump transistor MnU, connected between the intermediate node INT and the fourth internal node Downi, and which has a fourth control terminal NgD. The fourth pump transistor MnD is hence an N-channel MOS transistor, the gate terminal of which corresponds to the aforementioned fourth control terminal NgD. In addition, one of the conduction terminals of the fourth pump transistor MnD is connected to the fourth internal node Downi, whilst the other is connected to the intermediate node INT.
Note that, even though there have been described only the portions of the first and second charge-pump stages CBi-1, CBi that, as described in greater detail hereinafter, are involved in operations of mutual charge sharing, and in particular there have been described only the portions of the first and second latch circuits Li-1, Li involved in these operations of charge sharing, the first and second latch circuits Li-1, Li are the same as one another. In other words, even though it is not shown in FIG. 1, the first latch circuit Li-1 includes a fifth pump transistor and a sixth pump transistor, both of the same type as the third and fourth pump transistors MnU, MnD, whilst the second latch circuit Li further includes a seventh pump transistor and an eighth pump transistor, both of the same type as the first and second pump transistors MpU and MpD. By way of explanation, FIG. 2 shows a generic latch circuit L, formed by a first pair of transistors 2 and a second pair of transistors 4 connected in parallel. The first pair of transistors 2 is formed by two N-channel MOS transistors connected in series, whilst the second pair of transistors 4 is formed by two P-channel MOS transistors connected in series. FIG. 2 also illustrates the intermediate node INT and a further intermediate node INT′, the latter designed to enable connection of the generic latch circuit L to a charge-pump stage, or else to the supply voltage Vdd.
Once again with reference to the charge pump 1, it further includes a stabilization stage 6, which in turn is formed by a number n of stabilization circuits. In greater detail, assuming that the charge pump 1 is formed by a number N of charge-pump stages, the charge pump 1 includes a number n of stabilization circuits equal to twice the number N of charge-pump stages. By way of example, FIG. 1 shows a first stabilization circuit and a second stabilization circuit, designated, respectively, by 10p and 10n. 
In detail, the first stabilization circuit 10p includes in turn a first biasing capacitor Cbp1, connected between the first control terminal PgU and the second enable terminal FN, and a second biasing capacitor Cbp2, connected between the second control terminal PgD and the first enable terminal FX.
In addition, the first stabilization circuit 10p includes a first control transistor Mp1, connected between the first control terminal PgU and the intermediate node INT, and a second control transistor Mp2, connected between the second control terminal PgD and the intermediate node INT. In greater detail, the first and second control transistors Mp1, Mp2 are of the same type as the first and second pump transistors MpU, MpD.
As illustrated in FIG. 1, the first and second control transistors Mp1, Mp2 are P-channel MOS transistors. In addition, the gate terminal of the first control transistor Mp1 is connected to the second control terminal PgD, whilst one of the conduction terminals of the first control transistor Mp1 is connected to the intermediate node INT, and the other is connected to the first control terminal PgU. Furthermore, the gate terminal of the second control transistor Mp2 is connected to the first control terminal PgU, whilst one of the conduction terminals of the second control transistor Mp2 is connected to the intermediate node INT, and the other is connected to the second control terminal PgD. In addition, as illustrated once again in FIG. 1, the first and second control transistors Mp1, Mp2 can have respective bulk terminals, which can be connected to the intermediate node INT.
Likewise, the second stabilization circuit 10n includes a third biasing capacitor Cbn1, connected between the third control terminal NgU and the first enable terminal FX, and a fourth biasing capacitor Cbn2, connected between the fourth control terminal NgD and the second enable terminal FN.
The second stabilization circuit 10n further includes a third control transistor Mn1, connected between the third control terminal NgU and the intermediate node INT, and a fourth control transistor Mn2, connected between the fourth control terminal NgD and the intermediate node INT. In greater detail, the third and fourth control transistors Mn1, Mn2 are of the same type as the third and fourth pump transistors MnU, MnD.
As illustrated in FIG. 1, the third and fourth control transistors Mn1, Mn2 are N-channel MOS transistors. In addition, the gate terminal of the third control transistor Mn1 is connected to the fourth control terminal NgD, whilst one of the conduction terminals of the third control transistor Mn1 is connected to the intermediate node INT, and the other is connected to the third control terminal NgU. Furthermore, the gate terminal of the fourth control transistor Mn2 is connected to the third control terminal NgU, whilst one of the conduction terminals of the fourth control transistor Mn2 is connected to the intermediate node INT, and the other is connected to the fourth control terminal NgD.
In general, the first, second, third, and fourth pump capacitors CUpi-1, CDowni-1, CUpi, and CDowni can have one and the same first nominal capacitance. Likewise, the first, second, third, and fourth biasing capacitors Cbp1, Cbp2, Cbn1 and Cbn2 can have one and the same second nominal capacitance. In addition, all the transistors present in the charge pump 1 can be of the low-voltage type.
In use, the charge pump 1 is supplied by connecting the input terminal IN to a first reference voltage, for example the supply voltage Vdd. In addition, the output terminal OUT is connected to a load (not shown), which is connected not only to the output terminal OUT, but also to a second reference voltage, for example ground. In greater detail, to cause the charge pump 1 to supply energy to the load itself, supplied to the charge pump 1, respectively through the first enable terminal FX and the second enable terminal FN, are a first enable signal sFX and a second enable signal sFN, which are both typically voltage signals and are generated, for example, by a provided generator 8 (FIG. 1), connected to the first enable terminal FX and to the second enable terminal FN.
Generally, the first and second enable signals sFX, sFN are periodic with one and the same period T, and moreover each of them assumes, alternatively, a maximum value Vmax or a minimum value Vmin such that the absolute value of the difference between the maximum value Vmax and the minimum value Vmin is higher than the threshold voltage of the transistors (both the pump transistors and the control transistors) of the charge pump 1, and lower than the breakdown voltage of the transistors (both the pump transistors and the control transistors) of the charge pump 1. In what follows, it is assumed, by way of example, that the maximum value Vmax and the minimum value Vmin are equal, respectively, to the supply voltage Vdd and ground.
In greater detail, the first and second enable signals sFX, sFN are such as to be, ideally, in phase opposition. In other words, for each instant t, the first and second enable signals sFX, sFN assume different values. Again in other words, within a period T considered, it is possible to define a first subperiod and a second subperiod, which are consecutive to one another and are such that, during the first subperiod, the first and second enable signals sFX, sFN are, respectively, equal to Vdd and 0 (or vice versa), whilst during the second subperiod they are, respectively, equal to 0 and Vdd (or vice versa). The first and second subperiods can have the same duration.
An example of the (ideal) time plot of the first and second enable signals sFX, sFN is illustrated in FIG. 3, which shows two consecutive periods of the first and second enable signals sFX, sFN.
At each instant t, the charge pump 1 is alternatively in a first operating condition or a second operating condition. In particular, having assumed that Vmax=Vdd and Vmin=0, and recalling that the first and second enable signals sFX, sFN are in phase opposition, the first operating condition occurs when the value assumed by the first enable signal sFX is equal to 0, and the value assumed by the second enable signal sFN is equal to Vdd. Instead, if the values assumed, respectively, by the first and second enable signals sFX, sFN are equal to Vdd and 0, the second operating condition arises. It follows that, within each period T, there occurs a change of operating condition between the first subperiod and the second subperiod.
In what follows, in order to describe the first and second operating conditions, it is assumed that the first, second, third, and fourth internal nodes Upi-1, Downi-1, Upi, Downi have, respectively, a voltage VcUi-1, a voltage VcDi-1, a voltage VcUi, and a voltage VcDi, and that the first, second, third, and fourth control terminals PgU, PgD, NgU and NgD have, respectively, a voltage VPgU, a voltage VPgD, a voltage VngU, and a voltage VNgD. In addition, it is assumed that the intermediate node INT has a voltage Vi.
In detail, it may be shown that, in passing from the second operating condition to the first operating condition, the voltage VPgU passes from a value approximately equal to Vi-Vdd to a value approximately equal to Vi, whilst the voltage VPgD passes from a value approximately equal to Vi to a value approximately equal to Vi-Vdd. In addition, in passing from the second operating condition to the first operating condition, the voltage VcUi-1 and the voltage VcDi-1 undergo, respectively, a decrease and an increase, going to respective values such that, given the values accordingly assumed by the voltages VPgU and VPgD, the first pump transistor MpU is off, whilst the second pump transistor MpD is on.
Once again with reference to the passage from the second operating condition to the first operating condition, it may be shown that the voltage VNgD passes from a value approximately equal to Vi to a value approximately equal to Vi+Vdd, whilst the voltage VNgU passes from a value approximately equal to Vi+Vdd to a value approximately equal to Vi. In addition, in passing from the second operating condition to the first operating condition, the voltage VcUi and the voltage VcDi undergo, respectively, an increase and a decrease, going to respective values such that, given the values accordingly assumed by the voltages VNgU and VNgD, the third pump transistor MnU is off, whilst the fourth pump transistor MnD is on.
In practice, when the charge pump 1 is in the first operating condition, there occurs a charge sharing between the second pump capacitor CDowni-1 and the fourth pump capacitor CDowni; instead, between the first pump capacitor CUpi-1 and the third pump capacitor CUpi, charge sharing is prevented.
In a way similar to what has been described as regards the first operating condition, it may be shown that, when the charge pump 1 is in the second operating condition, the voltages VNgU, VNgD, VPgU, VPgD, VcUi-1, VcDi-1, VcUi and VcDi are such that the first pump transistor MpU and the third pump transistor MnU are on, whilst the second and fourth pump transistors MpD, MnD are off.
In detail, it may be shown that, in passing from the first operating condition to the second operating condition, the voltage VPgU passes from a value approximately equal to Vi to a value approximately equal to Vi-Vdd, whilst the voltage VPgD passes from a value approximately equal to Vi-Vdd to a value approximately equal to Vi. In addition, the voltage VNgD passes from a value approximately equal to Vi+Vdd to a value approximately equal to Vi, whilst the voltage VNgU passes from a value approximately equal to Vi to a value approximately equal to Vi+Vdd. Finally, in passing from the first operating condition to the second operating condition, the voltage VcUi-1 and the voltage VcDi-1 undergo, respectively, an increase and a decrease, whilst the voltage VcUi and the voltage VcDi undergo, respectively, a decrease and an increase.
In practice, when the charge pump 1 is in the second operating condition, there occurs a charge sharing between the first and third pump capacitors CUpi-1, CUpi; instead, between the second and fourth pump capacitors CDowni-1, CDowni, charge sharing is prevented.
By way of example, FIG. 4 illustrates the time plots of the voltages VcDi-1, VPgD, Vi, VcDi and VNgD, where the changes thereof at the passage from the second operating condition to the first operating condition, and vice versa, are highlighted. In particular, it is assumed that the first and second enable signals sFX and sFN have a frequency of 120 MHz.
Operatively, the voltage Vi of the intermediate node INT remains approximately constant, irrespective of the operating condition. In addition, within each subperiod, the potentials VPgU, VPgD, VNgU, VNgD remain to a first approximation constant. Consequently, within each subperiod, and hence throughout the duration of each charge sharing between the first and third pump capacitors CUpi-1, CUpi, or else between the second and fourth pump capacitors CDowni-1, CDowni, the states (on or off) of the first, second, third, and fourth pump transistors MpU, MpD, MnU, MnD do not change. In practice, the first, second, third and fourth control transistors Mp1, Mp2, Mn1, and Mn2 enable first, second, third, and fourth biasing capacitors Cbp1, Cbp2, Cbn1, Cbn2 to update respective charge states continuously, in addition to recovering any possible charge lost in driving the first, second, third, and fourth pump transistors MpU, MpD, MnU and MnD. It follows that charge sharing, and in general operation of the charge pump 1, is optimal, even in the case where the supply voltage Vdd is not particularly high.
In particular, due to the possibility of using transistors of the low-voltage type, and due to the presence of just two operating conditions, the charge pump 1 can operate at frequencies higher than 100 MHz, and can moreover function with supply voltages Vdd that are not necessarily high. For example, known to the art are charge pumps of the type described operating with supply voltages Vdd close to 1 V.
As shown in FIG. 5, the charge pump 1 can moreover include a first logic inverter and a second logic inverter, designated, respectively, by INV1 and INV2. In detail, the first logic inverter INV1 is connected between the third biasing capacitor Cbn1 and the second enable terminal FN so as to be set in series with the third biasing capacitor Cbn1 itself. Instead, the second logic inverter INV2 is connected between the fourth biasing capacitor Cbn2 and the first enable terminal FX so as to be set in series with the fourth biasing capacitor Cbn2 itself.
It may be shown that, due to the presence of the first and second logic inverters INV1, INV2, operation of the charge pump 1 remains optimal even in the case where the first and second enable signals sFX, sFN are not perfectly in phase opposition; i.e., they assume, in certain time intervals, one and the same value.
As shown in FIG. 6, the charge pump 1 can include a plurality of bulk-biasing circuits, only one of which is shown in FIG. 6, where it is designated by 11. In practice, there are present as many bulk-biasing circuits as the P-channel MOS transistors present in the latch circuits of the charge pump 1, the P-channel MOS transistors provided with respective bulk terminals. Described in what follows is just the bulk-biasing circuit 11 for the first pump transistor MpU.
In particular, the first pump transistor MpU is provided with a bulk terminal of its own, to which the bulk-biasing circuit 11 is connected. In addition, the bulk-biasing circuit 11 is connected to the first control terminal PgU and to the intermediate node INT.
As shown in yet greater detail in FIG. 7, the bulk-biasing circuit 11 includes a first biasing transistor Mb1, a second biasing transistor Mb2, and a third biasing transistor Mb3, which are P-channel MOS transistors.
In detail, the first biasing transistor Mb1 has the gate terminal connected to the first control terminal PgU, and moreover has one of the respective conduction terminals connected to the first internal node Upi-1, and the other conduction terminal connected to a bulk node B. The gate terminal of the second biasing transistor Mb2 is connected to the first internal node Upi-1, whilst one of the conduction terminals of the second biasing transistor Mb2 is connected to the bulk node B, and the other is connected to the third internal node Upi. Furthermore, the gate terminal of the third biasing transistor Mb3 is connected to the third internal node Upi, whilst one of the conduction terminals of the third biasing transistor Mb3 is connected to the bulk node B, and the other is connected to the first internal node Upi-1.
The first, second, and third biasing transistors Mb1, Mb2, Mb3 possess respective bulk terminals, which are all connected to the bulk node B.
Operatively, the bulk-biasing circuits prevent onset of the so-called “latchup” phenomenon within the P-channel MOS transistors forming part of the latch circuits of the charge pump 1, the phenomenon being due to the presence of parasitic transistors within the P-channel MOS transistors themselves. In fact, the bulk-biasing circuits cause the bulk terminals of the P-channel MOS transistors to be kept at voltages such that the aforementioned parasitic transistors will be off.
The charge pump 1 represents a considerable improvement as compared to previously known charge pumps, which were able to operate at frequencies not higher than 50 MHz and required high supply voltages Vdd. However, there exist situations in which operation of the charge pump 1 may prove non-optimal.
For example, when the charge pump 1 is off, i.e., when the first and second enable terminals FX, FN are connected to ground, the first, second, third, and fourth biasing capacitors Cbp1, Cbp2, Cbn1 and Cbn2 are discharged towards ground. The discharge can occur in such a way that, at an instant tx, three of the aforementioned biasing capacitors, for example the first, second, and third biasing capacitors Cbp1, Cbp2, Cbn1, are at one and the same first intermediate voltage Vx1, whilst a remaining biasing capacitor, for example the fourth biasing capacitor Cbn2, is at a second intermediate voltage Vx2>Vx1+Vdd.
Consequently, if at the instant tx the charge pump 1 is turned back on, for example to send the charge pump 1 to the second operating condition, hence bringing the first enable terminal FX to the supply voltage Vdd, the voltage VNgU does not exceed the voltage VNgD, in such a way that the fourth control transistor Mn2 remains off, thus not enabling discharge of the fourth biasing capacitor Cbn2. In fact, the voltage VNgD is such that the third control capacitor Mn1 remains on, with the consequence that the voltage VNgU remains equal to Vi.
It thus follows that, once the charge pump 1 is turned back on, the voltage VNgD remains stably (i.e., irrespective of the operating condition in which the charge pump 1 finds itself) higher than the voltages VcDi and VcUi, and hence the fourth pump transistor MnD remains stably on, irrespective of the operating condition in which the charge pump 1 finds itself.
It follows that, after turning back on, when the charge pump 1 is in the second operating condition, in which there should in theory occur charge sharing between the first and third pump capacitors CUpi-1, CUpi, there occurs in actual fact a charge sharing between the first, third, and fourth pump capacitors CUpi-1, CUpi, CDowni, with consequent decay of the level of performance of the charge pump 1, and in particular with consequent reduction of the output current IL. In addition, the fact that the third control transistor Mn1 remains stably on leads to the third biasing capacitor Cbn1 discharging to the voltage Vi, and hence to the voltage VNgU not being sufficient to turn the third pump transistor MnU on. Consequently, the charge sharing between the first and third pump capacitors CUpi-1, CUpi is limited also by the failure of the third pump transistor MnU to switch on, or in any case by imperfect switching-on thereof.
A further example of non-optimal operation of the charge pump 1 arises when the charge pump 1 is off, and discharge of the first, second, third, and fourth biasing capacitors Cbp1, Cbp2, Cbn1 and Cbn2 occurs in such a way that the second, third, and fourth biasing capacitors Cbp2, Cbn1, Cbn2 go to one and the same third intermediate voltage Vx3, whilst the first biasing capacitor Cbp1 goes to a fourth intermediate voltage Vx4<Vx3−Vdd.
In said conditions, if the charge pump 1 is turned back on, the voltage VPgU is such that the second control transistor Mp2 is always on, and hence the voltage VPgD is once again equal to Vi, so preventing turning-on of the first control transistor Mp1, even when the second enable terminal FN is set at Vdd. Consequently, the first biasing capacitor Cbp1 never discharges.
Hence, once the charge pump 1 is turned back on, the first pump transistor MpU remains stably on, irrespective of the operating condition in which the charge pump 1 finds itself. It follows that, after turning back on, when the charge pump 1 is in the first operating condition, in which there should in theory occur charge sharing between the second and fourth pump capacitors CDowni-1, CDowni, there occurs in actual fact a charge sharing between the first, second, and fourth pump capacitors CUpi-1, CDowni-1, CDowni, with consequent decay of the level of performance of the charge pump 1. In addition, when the charge pump 1 finds itself in the first operating condition, it is found that the voltage VPgD is such as not to enable turning-on of the second pump transistor MpD, and hence the charge sharing between the second and fourth pump capacitors CDowni-1, CDowni is limited also by the failure of the second pump transistor MpD to switch on, or in any case by imperfect switching-on thereof, thus further reducing the output current IL supplied to the load by the charge pump 1.
In general, it is moreover possible that, in the situations described previously, turning back on of the charge pump 1 causes breakdown of one or more oxide layers present within the first, second, third, and fourth pump transistors MpU, MpD, MnU, MnD.